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W83303AD/W83303AG
Winbond Advanced ACPI Controller W83303AD/W83303AG
W83303AD/W83303AG
W83303AD/AG Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 N.A. N.A. N.A. 12,13,14 10/25/04 12/20/04 1/09/06 0.5 0.51 0.52 Dates Version Version on Web N.A. N.A. N.A. N.A. Main Contents All of the versions before 0.50 are for internal use. First published preliminary version. Add part no of W8303AG with Pb-free package. Modified the application circuit.
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83303AD/W83303AG
1. GENERAL FUNCTION DESCRIPTION
Provides Voltages - 5V Active/Sleep (5VDUAL) - Programmable 5VDL/5VSTR/5VCC for USB Devices(5VUSB) - 3.3V Active/Sleep (3.3VDUAL) - Programmable Dual-Channels RAM Active/Sleep (VSTR) for DDR - Auto-detective 2.6VSTR/1.8VSTR for DDR/DDRII Voltage - Two Programmable Linear Regulators and one Linear Regulator Ranging 1.2V~5.00V for Over-Clocking Application - 1.2V VCCVID for Intel(R) P4 CPU or FSB_VTT for Grandsdale - 1.5V VPCI Voltage Supports VRGOOD signal for Intel(R) P4 CPU Power Good Control Supports RSMRST# Signal Control Provides Signals for ATX Power Supply PS_ON# Control I2C Interface Selectable I2C Address Internal Charge Pump Support Up to 9.5VSB Drive All N-Channel MOSFET Soft Start Under-Voltage Monitoring for 3VDUAL, VPCI and VRAM Channels
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Publication Release Date: Jan. 9, 2006 Revision 0.52
W83303AD/W83303AG
2. W83303AD/AG PIN-OUT
VPCI_DRV
VPCI_SEN
1.2V_DRV
1.2V_SEN
26
LR1_DRV
36
35
34
33
32
31
30
29
28
27
LR1_SEN LR2_DRV LR2_SEN DDRDET# FAULT# PS_IN# PW_BUT# PS_OUT# DGND PWR_OK A0 D5VSB
37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12
VRGOOD
25 24 23 22 21 20 19
CHRPMP
AGND
5VSB
VCC
C2
C1
AGND VRAM_DRV1 I_SEN1 VRAM_SEN VRAM_DRV2 I_SEN2 5VSB ISET SS VCC3 3.3VSB_DRV 3.3V_SEN
W83303AD/AG
18 17 16 15 14 13
PWM_MODE
I2C_DATA
5VSBDRV
S3#
S5#
LR3_SEN
AGND
-2-
3V/5VDRV
I2C_CLK
RSMRST#
LR3_DR V
5VUSB
W83303AD/W83303AG
3. PIN DESCRIPTIONS
NO NAME I/O FUNCTION DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S3# S5# I2C_DATA I2C_CLK RSMRST# PWM_MODE LR3_SEN LR3_DRV AGND 5VUSB 5VSBDRV 5VDRV 3.3V_SEN 3.3VSB_DRV VCC3 SS
I I
SYSTEM ACPI CONTROL SIGNALS
I/O I2C Interface, and the default ID value are defined as 5CH (0101 110X) as I well as 5EH (0101 111X), and X is used to control read/write. OD I I A signal to indicate 3VDUAL power status. The signal will be issued after 82ms delay when the level of 3VDUAL higher than 2.8V 0=Internal RAM for Linear Mode; 1= external RAM for PWM Mode
Linear Regulators ranging form 1.2V to 5V and can be adjusted by O external resistors P Power ground O O O I O 3.3VDUAL Voltage regulator Power switch for USB devises provides a programmable Voltage (5VDUAL/5VSTR/ 5VCC) for USB devices. It can be set by register CR00
P Power 3.3Vcc I Soft-Start pin. Attach a capacitor to this pin to determine the soft-start rate; and the slew-rate of SS is set by adjust the capacity of the external capacitor. Attached a specific external resistor to determine the internal reference current.
17 18 19 20 21 22 23 24 25
ISET 5VSB I_SEN2 VRAM_DRV2 VRAM_SEN I_SEN1 VRAM_DRV1 AGND VRGOOD
I
P Power Pin I O I I O P Power ground OD The signal is applied for the Intel(R) Northwood CPU using; it's a signal to declare the CPU VID status. 2 channels of VSTR output for DDR or DDRII with internal current sharing design to balance the current on the channels. In which I_SEN1 & I_SEN2 pins should be connected together to 5VSB or 3VDUAL if only one channel used. The DDR or DDRII determine by DDRDET#. If DDRDET# =0 VRAM=DDR(2.6V) ; DDRDET#=1 VRAM=DDRII(1.8V).
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Publication Release Date: Jan. 9, 2006 Revision 0.52
W83303AD/W83303AG
Pin Descriptions, continued
NO
NAME
I/O
FUNCTION DESCRIPTION
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1.2V_SEN 1.2V_DRV 5VSB C1 C2 CHRPMP AGND VPCI_DRV VPCI_SEN VCC LR1_DRV LR1_SEN LR2_DRV LR2_SEN DDRDET#
I O I I P P
1.2VCC voltage regulator for Intel(R) P4 CPU application.
P Power Pin Charge pump pins. It supports 10mA driving current and insures output voltage 9V or above. Power pin
O 1.5V Voltage Regulator for PCI Express. If this power plane won't be used, the VPCI_SEN must be connected to 3VDUAL to avoid the fault I trigger of LUV event. P Power pin O Linear Regulators ranging form 1.2V to 5V and can be adjusted by O external resistors I I A signal to indicate type of DDRRAM that plugged- in; low means 2.6V for DDR and high means 1.8V for DDRII. Fault event be monitored; the chip shut the ATX power supply down directly by control the PS_ON# signal as long as the fault events are triggered. Power on signal. Low active. I System PW_BUT for power sequence monitoring. O Pin to control ATX power supply. P Power ground. I I Power good input signal of ATX power supply. I2C address selecting pin. I
41 42 43 44 45 46 47 48
FAULT# PS_IN# PW_BUT# PS_OUT# DGND PWR_OK A0 D5VSB
I
P Power pin.
*VRGOOD & TYPEDET# can endure 0-12V level voltage.
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W83303AD/W83303AG
4. INTERNAL BLOCK DIAGRAM
PWR_OK C1 C2 CHRPMP PW_BUT# S3# S5# DDRDET# RSMRST# PS_IN# FAULT# PS_OUT# VRGOOD 1.2V_DRV 1.2V_SEN SS ISET VPCI_DRV VPCI_SEN Soft Start Reference Current 1.20V PCI express 1.5V Control Register Reset Integrated Circuit 3.3V_SEN Control Circuit 3.3VDL 3.3V_DRV
Charge Pump
1.2V VCCVID
5VDL
5VDRV 5VSBDRV 5VUSB VRAM_DRV1 I_SEN11 VRAM_SEN1
5VUSB
VRAM
VRAM_DRV2 I_SEN2 EXT_RAM I2C_CLK I2C_DATA A0
I2C
LR_SEN1
LR_SEN2
LR_SEN3
LR_DRV1
LR_DRV2
LR_DRV3
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Publication Release Date: Jan. 9, 2006 Revision 0.52
W83303AD/W83303AG
5. I2C COMMUNICATION PROTOCOL
The W83303AD/AG serial protocol accepts byte write, byte read operation from the controller. For the byte write and byte read operations, the system controller can access individual indexed bytes. The byte write and byte read protocol is outlined in following table. Besides, the slave receiver address is 0101 1110(5Eh).
BYTE WRITE BIT 1 2:8 9 10 DESCRIPTION BIT 1 2:8 9 10 BYTE READ DESCRIPTION
Start Slave address - 7 bits Write Acknowledge from Slave Command Code - 8 bits `1xxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop
Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `1xxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7bits Read Acknowledge from slave Data byte from slave - 8bits Not Acknowledge Stop
11:18
11:18
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
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W83303AD/W83303AG
6. REGISTER DESCRIPTION 6.1 CR00 (5VUSB Setting Register, Default 0x00h, Read/Write)
BIT1 BIT0 SUPPORT ACPI STATE
0 0 1
1 0 1
S0, S3 S0, S3, S5 S0
6.2
CR01 (VPCI Voltage Setting Register, Default 0x00h, Read/Write)
BIT2 BIT1 BIT0 VAGP OUTPUT
Bit7~3: Reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1.50V 1.55V 1.60V 1.65V 1.70V 1.80V 1.90V 2.00V
6.3
CR02 (VRAM Voltage Setting Register, Default x000 0000 b, Read/Write)
Bit7 is reserved for signal DDRDET# Setting (Dynamic detect) DDRDET#=H bit7=1 DDRII type, DDRDET#=L bit7=0 DDRI type. Bit3,2, 1 and 0 are applied for DDRRAM output adjusting.
BIT7 BIT3 BIT2 BIT1 BIT0 VRAM OUTPUT
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
2.60V 2.50V 2.55V 2.65V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V
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W83303AD/W83303AG
BIT7
BIT3
BIT2
BIT1
BIT0
VRAM OUTPUT
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 1
0 0 0 1 1 1 1 0 0
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1
1.75V 1.85V 1.90V 1.95V 2.00V 2.05V 2.10V 2.20V 2.30V
6.4
CR03 (Linear Regulator 1,2 Voltage Setting Register, Default 0x00h, Read/Write)
BIT1 BIT0 PERCENTAGE OF VOLTAGE INCREASE
VLR1: Bit2, 1 and 0 are applied for output voltage adjusting.
BIT2
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 1 0 1
+0% +2% +4% +8% +12% +16%
VLR2 : Bit2, 1 and 0 are applied for output voltage adjusting.
BIT6 BIT5 BIT4 PERCENTAGE OF VOLTAGE INCREASE
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 1 0 1
+0% +2% +4% +8% +12% +16%
6.5
Bit 7-0
CR04 Chip ID
Name CHIPID[7:0] Read/Write Read Only Description Winbond Chip ID number. Read this register will return 0xa1h for W83303AD/AG.
Power on default [7:0] = 1010,0001 b
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W83303AD/W83303AG
6.6 CR05 (Linear-Under-Voltage Setting Register) default 0x07
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5
Bit0, 1 and 2 are applied for Linear-Under-Voltage Protection functions enable/disable. 1/0 1/0 1/0 1/0 1/0 1/0 Enable/disable VPCI LUV, default value=1 Enable/disable VRAM LUV, default value=1 Enable/disable Dual3.3V LUV, default value=1 Enable/disable RSRMST# restart as release latching fault or LUV event Default value = 0 (disable) Enable/disable Power Button release latching fault event. Default value = 0 (disable) Enable/disable Power Button release latching LUV event. Default value = 0 (disable)
6.7
Bit 7-0
CR06 Version ID
Name CHIPID[7:0] Read/Write Read Only Description Winbond Version ID number. Read this register will return 0x00h for W83303AD/AG.
Power on default [7:0] = 0000,0000 b
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Publication Release Date: Jan. 9, 2006 Revision 0.52
W83303AD/W83303AG
7. ELECTRICAL SPECIFICATION 7.1 AC CHARACTERISTICS
Vcc=5V 5 %, TA = 0C to +70C
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
VPCI Linear Regulator Nominal Output Voltage Regulation Under-Voltage Falling Threshold VPCI_DRV Output Voltage Vref Voltage Reference Nominal Output Voltage 1.2V Linear Regulator Nominal Output Voltage VRGood delay VRAM Regulator Nominal Output Voltage Nominal Output Voltage Regulation Under-Voltage Falling Threshold MAX VRAM_DRV Output Voltage Nominal Output Voltage Nominal Output Voltage Nominal Output Voltage Nominal Output Voltage Nominal Output Voltage Nominal Output Voltage Soft Start Source current Soft start current 20 uA 8 70 2.60 1.80 4 V V % % V I(VRAM_DRV) < 0.3mA CR02(bit7)=0 CR02(bit7)=1 1.152 1.2 2 1.248 V mS After 1.2V_SEN>1.1V 1.152 1.2 1.248 Iload < 1mA 8 70 1.50 4 V % % V I(VPCI_DRV) < 0.3mA CR01(bit2~0)=000
Increase percentage of Linear Regulator _1,2 output voltage (%) 0 2 4 8 12 16 % % % % % %
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W83303AD/W83303AG
AC CHARACTERISTICS, continued
5VDUAL Switch Controller 5VDRV Output High Voltage 5VSBDRV Output High Voltage 5VUSB Output High Voltage 5VUSB SS Sourcing Current 3.3VDUAL Under-Voltage Falling Threshold MAX 3VSBDRV Output Voltage Charge Pump Charge Pump Frequency Charge Pump Voltage 9.5 200 KHz 9 70 % V I(3VSBDRV) < 0.3mA 9 9 9 2.5 uA Cap Loading Cap Loading Cap Loading @ Soft-start
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Publication Release Date: Jan. 9, 2006 Revision 0.52
W83303AD/W83303AG
8. APPLICATION CIRCUIT 8.1 Linear Mode
5VSB 5VSB DUAL/VSB/VSTR/VCC 5VSB R3 W5VSB 5 C2 0.1U C3 0.1U DDRDET# FAULT# PS_IN# PS_OUT#(to ATX) PWR_OK(from ATX) W5VSB C7 10U VLR3=1.2X(R8+R10)/ R10 MOSFET N Q3 2 C11 1000U C12 1000U 5VDUAL C14 10U 5VUSB MOSFET N Q5 2 3 C20 1000U C21 1000U 1 R10 R 3 R8 R R9 4.7K RSMRST# LR3_DRV S3# S5# SDA SCL R11 1K 1 2 3 4 5 6 7 8 9 10 11 12 5VSB 48 47 46 45 44 43 42 41 40 39 38 37 LR3_DRV R7 R VCC5 C13 0.1U VCC3 Q4 NMOS C15 C18 0.1U 0.1U VCC3 MOSFET N Q6 W5VSB VRGOOD R12 4.7K C23 1000U C24 1000U C19 10U 1.2V C16 1000U C17 1000U VPCI C10 0.1U 1 A0 R5 R R1 4.7K R2 4.7K MOSFET N Q1 C1 10U VLR2=1.2X(R4+R5)/ R5 DUAL/VSB/VSTR/VCC C4 R4 R 1000U C5 1000U C6 10U VLR1=1.2X(R6+R7)/ R7 Q2 MOSFET N
DUAL/VSB/VSTR/VCC
R6 R
C8 1000U
C9 1000U
D5VSB A0 PWR_OK DGND PS_OUT# PW_BUT# PS_IN# FAULT# DDRDET# LR2_SEN LR2_DRV LR1_SEN
3.3V_SEN 3.3VSB_DRV VCC3 SS ISET 5VSB I_SEN2 VRAM_DRV2 VRAM_SEN I_SEN1 VRAM_DRV1 AGND
S3# S5# I2C_DATA I2C_CLK RSMRST# PWM_MODE LR3_SEN LR3_DRV AGND 5VUSB 5VSBDRV 3V/5VDRV
W83303AD
LR1_DRV VCC VPCI_SEN VPCI_DRV AGND CHRPMP C2 C1 5VSB 1.2V_DRV 1.2V_SEN VRGOOD
36 35 34 33 32 31 30 29 28 27 26 25 C22 0.1U
13 14 15 16 17 18 19 20 21 22 23 24
5VSB C25 10U VCC5 1 5VDUAL Q8 MOSFET N 3 C32 1000U C33 1000U MOSFET N 2 Q9 VCC3 1 MOSFET N Q10 Q11 5VSB
VCC3/1.2V
3VDUAL Q7 MOSFET N
C26 10U R14 4m VRAM
C27 10U C30 2 MOSFET N 0.33U Q12 MOSFET N R13 100K 3VDUAL C28 1000U C31 10U C29 1000U R15 4m
3VDUAL C34 0.1U
3
VCC3 C35 C36 1000U 1000U W5VSB C37 0.1U
VRAM VRAM 1 R16 1K C38 1500U 2 3 R19 1K C39 1n 4 U1 VIN GND VREF VOUT VCNTL VCNTL VCNTL VCNTL 8 7 6 A0 3VDUAL
A0=HIGH, I2C Add=0X5EH
R17 4.7K 5VSB
DDRDET#=HIGH, VRAM=1.8V
R18 DDRDET# 4.7K 5VSB
A0=LOW, I2C Add=0X5CH
5 R20 C40 0.1U A0 1K
DDRDET#=LOW, VRAM=2.6V
R21 DDRDET# 1K
W83310S-R2/DS VTT C41 R22 0.1U 1K C42 1000U
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W83303AD/W83303AG
8.2 PWM Mode
5VSB 5VSB DUAL/VSB/VSTR/VCC 5VSB R3 W5VSB 5 C2 0.1U C3 0.1U DDRDET# FAULT# PS_IN# PS_OUT#(to ATX) PWR_OK(from ATX) W5VSB C7 10U VLR3=1.2X(R10+R113)/ R13 MOSFET N Q3 2 C11 1000U C12 1000U 5VDUAL C14 10U 5VUSB MOSFET N Q4 2 3 C19 1000U C20 1000U 1 R13 R 3 R10 R R12 4.7K RSMRST# LR3_DRV R11 4.7K S3# S5# SDA SCL 1 2 3 4 5 6 7 8 9 10 11 12 5VSB 48 47 46 45 44 43 42 41 40 39 38 37 LR3_DRV R9 R VCC5 C13 0.1U C10 0.1U 1 A0 R6 R R1 4.7K R2 4.7K MOSFET N Q1 C1 10U VLR2=1.2X(R4+R6)/ R6 DUAL/VSB/VSTR/VCC C4 R4 R 1000U C5 1000U C6 10U VLR1=1.2X(R7+R9)/ R9 R5 Q2 MOSFET N A0 4.7K 5VSB
A0=HIGH, I2C Add=0X5EH
DUAL/VSB/VSTR/VCC
R7 R
C8 1000U
C9 1000U
A0=LOW, I2C Add=0X5CH
R8 A0 4.7K
D5VSB A0 PWR_OK DGND PS_OUT# PW_BUT# PS_IN# FAULT# DDRDET# LR2_SEN LR2_DRV LR1_SEN
3.3V_SEN 3.3VSB_DRV VCC3 SS ISET 5VSB I_SEN2 VRAM_DRV2 VRAM_SEN I_SEN1 VRAM_DRV1 AGND
S3# S5# I2C_DATA I2C_CLK RSMRST# PWM_MODE LR3_SEN LR3_DRV AGND 5VUSB 5VSBDRV 3V/5VDRV
W83303AD
LR1_DRV VCC VPCI_SEN VPCI_DRV AGND CHRPMP C2 C1 5VSB 1.2V_DRV 1.2V_SEN VRGOOD
36 35 34 33 32 31 30 29 28 27 26 25 C21 0.1U
DDRDET#=HIGH, VRAM=1.8V
VPCI_REF C16 C17 0.1U 0.1U C15 0.1U VCC3 C18 10U 1.2V VRGOOD R16 4.7K C22 1000U C23 1000U DDRDET# DDRDET# R14 4.7K 5VSB
MOSFET N Q5 W5VSB
DDRDET#=LOW, VRAM=2.6V
R15 4.7K
13 14 15 16 17 18 19 20 21 22 23 24
5VSB C24 10U VCC5 1 5VDUAL Q6 MOSFET N 3 C30 1000U C31 1000U MOSFET N Q7 VCC3 MOSFET N Q8 Q9 1 5VSB
VCC3/1.2V VRAM VRAM VRAM_REF 1 R18 1K C27 1500U 2 3 U1 VIN GND VREF VOUT VCNTL VCNTL VCNTL VCNTL 8 7 6 5 C32 0.1U 3VDUAL
C25 10U C28 2 MOSFET N
R17 100K 3VDUAL
C26 0.1U
2
R19 1K
C29 1n
4
3
3VDUAL C33 0.1U
W83310S-R2/DS 0.33U VTT VCC3 C34 R20 0.1U 1K C38 0.1U W5VSB C35 2000U
C36 C37 1000U 1000U
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Publication Release Date: Jan. 9, 2006 Revision 0.52
W83303AD/W83303AG
VRAM
5VDUAL C40 R23 4.7K 2.2U 5VDUAL R21 10 C41 2.2U 1 2 3 4 5 6 7 U2 LGATE VDD VDDA PWOK GNDA SS COMP ISEN GND HGATE BOOT BG_REF VREF FB 14 13 12 11 10 9 8 R25 33 R26 C47 0.1U R28 (OPT) R29 R30 5.1K(1%) 5.1K(1%) 49.9K C53 (OPT) C48 0.22U C49 2000U C50 1000U R22 5.6K C39 0.22U D1 SCHOTTKY NMOS Q10 L1 R24 2.2 C45 6.8n NMOS Q11 L2 5VDUAL 1.5U 3.3U
VRAM
C42 2.2U 5VDUAL
C43 2000U
C44 2000U
VRAM_REF
C46 0.1U
W83320S
C51 C52 2.2n
(OPT) R27 100k
VPCI
VPCI VCC5 R31 10 C55 R33 4.7K 2.2U C56 2.2U 1 2 3 4 5 6 7 U3 LGATE VDD VDDA PWOK GNDA SS COMP ISEN GND HGATE BOOT BG_REF VREF FB 14 13 12 11 10 9 8 R35 33 R36 C62 0.1U R38 (OPT) R39 5.1k 49.9K C68 (OPT) C63 0.22u C64 2000U C65 1000U NMOS Q12 L3 C54 0.22U D2 SCHOTTKY
VCC5
R32 5.6K
3.3U
C57 2.2U VCC5 NMOS Q13 L4
R34 2.2 C60 6.8n
C58 2000U
C59 2000U
VPCI_REF
C61 0.1U
VCC5 1.5U
W83320S
C66 C67 2.2n
(OPT) R37 100k R40 (OPT)
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W83303AD/W83303AG
9. ORDERING INSTRUCTION
PART NO. PACKAGE REMARKS
W83303AD W83303AG
48-pin LQFP 48-pin LQFP Pb-free package
10. HOW TO READ THE TOP MARKING
inbond
W83303AD 214658302 410GBRA
inbond
W83303AG 214658302 410GBRA
1st Line: Winbond Logo 2nd Line: Part No W83303AD, W83303AG (Pb-free package) 3rd Line: Wafer production serial number 4th Line: tracking code 410GBRA 410Date code, 410 means package was made in '04 week 10 GAssembly ID, G means GR, A means ASE...etc. BChip Version, A means version A, B means version B RAWinbond internal use
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Publication Release Date: Jan. 9, 2006 Revision 0.52
W83303AD/W83303AG
11. PACKAGE DIMENSION
D
HD
A A 2 A 1
36
25
37
24
HE E
48
13
1
SEATING PLANE Y
e
b
12
c
L L1
Controlling dimension: Millimeters
Symbol A A A b c D E e H H L L1 Y 0 0 D E 1 2 0.002 0.053 0.006 0.004 0.272 0.272 0.014 0.350 0.350 0.018 0.004 0.055 0.008 0.006 0.276 0.276 0.020 0.354 0.354 0.024 0.039 0.004 7 0 0.006 0.057 0.010 0.008 0.280 0.280 0.026 0.358 0.358 0.030 Dimension in inch Min Nom Max Dimension in mm No Max m 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.10 7 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75
Mi n
0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45
W83303AD/W83303AG
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: Jan. 9, 2006 Revision 0.52

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